1. Field of the Invention
The present invention generally relates to memory systems comprising a plurality of memory devices, and more particularly, to a memory system for removing a command/address clock which samples command/address signals is removed.
2. Description of the Prior Art
A clock control device of conventional memory devices comprises a register chip for buffering command/address input signals and a phase locked loop chip for generating timing signals, in case of dual in line memory module ‘DIMM’. When a plurality of PLL output clocks are generated in the PLL, a compensation capacitor (hereinafter, referred to as ‘Ccomp’) is used to control their edge timing.
FIG. 3 is a diagram illustrating an example of a conventional memory system using distributed command/address signals. A PLL circuit 20 edge controls address clocks ‘CACLK’ inputted from a controller 10 by using the Ccomp, which compensates signal delay generated from transmission lines, and adjusts the edge-controlled CACLKS to have the same phase with the CACLKs inputted from the controller 10, and then applies the adjusted CLK0, CLK1, CLK2 and CLK3, to a plurality of memory devices 61, 62, 63 and 64, respectively. Here, a register 30 buffers a plurality of command/address input signals ‘CAin’ outputted from the controller 10, and outputs a plurality of command/address output signals ‘CAout’ to the plurality of memory devices 61, 62, 63 and 64, respectively, via transmission lines.
However, the conventional memory system has the following problems. First, since the conventional memory system should include the transmission lines to transmit clocks CLK0–CLK3 to the plurality of memory devices, the lay-out of semiconductor device design becomes complicated. Second, since the memory devices receive clocks CLK0–CLK3 and write data capture clocks ‘WCLK’, clock domain collision can be generated between clocks and write data capture clocks. Third, since each memory device should comprise an individual PLL or DLL circuit, jitter and cost of the whole system are increase. Fourth, since a register and a PLL circuit should be embodied using separate chips, the packaging process of semiconductor devices is complicated, thereby the packaging cost is increased. Finally, timing margins are degraded due to differences of a plurality of compensation capacitors.